When creating new generations of memory designs, improvement in speed and reduction in power consumption of the memory are prime considerations. With the adoption of revolutionary pin-out configurations, where the corner power and ground pins have been moved to center positions on both sides of the chip and output pads have been moved from one side of the periphery to both sides, and with the greater density of new generations of memory chips increasing the routing line distance between memory cells and output pins, new design strategies are required to further improve the speed/power product of the memory.
FIG. 1 shows a prior art multiplexed output circuit for a multiple core memory array. Multiplexed output circuit 110 receives a global data line differential signal GDL1 13O/GDLB1 131 from a first memory core at amplifier 112. Multiplexed output circuit 110 receives a global data line differential signal GDL2 132/GDLB2 133 from a second memory core at amplifier 114. The differential signals provide a differential input into each amplifier, except when the sending core is deselected. Because multiplexed output circuit 110 reads from two separate cores, ENABLE1 134 and ENABLE2 135 are set to enable either amplifier 112 or amplifier 114, respectively, as each core is addressed and read. Amplifiers 112, 114 are generally located as close as possible to the sense amplifier reading data from a particular memory block. Therefore, a significant RC delay is introduced by the parasitic capacitance of the long routing lines driven by amplifiers 112, 114 to the corresponding output buffer 120. This can be seen in FIG. 1 where RC delays 116-119 represent the parasitic routing delay affecting the amplifier output signals 136-139. The resultant delayed signals DATA 140 and DATAB 141 are received at the output buffer 120, located at the periphery of the chip in proximity to the output driver 122 and data pad 124. Output buffer 120 often includes a rise/fall control 121 to introduce rise time and fall time components in the pull up signals 142 and pull down signals 143. These additional rise and fall times are introduced into the signals to prevent reflections, noise and glitches in the output driver signal DQ 144.
As will be appreciated, to maintain the speed performance of the output circuit, amplifiers 112 and 114 need increased switching current capability to drive larger parasitic routing components. This requires the amplifier, which is generally a DC current consuming device, to consume additional power to compensate for the increased parasitic routing delay seen for greater density memory arrays. Thus, multiplexed output circuits in the prior art do not provide the best speed-power product for new generations of higher density memory devices utilizing the revolutionary pin-out configurations.